--- /dev/null
+From 9d856aa1c81930a5d8df0e29d6cb0faa3fa87206 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Fri, 31 Oct 2025 16:58:24 +0100
+Subject: [PATCH] arm64: dts: rockchip: add eMMC CQE support for rk3588
+
+The RK3588 eMMC controller supports CQE, so add the missing
+DT flag.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://patch.msgid.link/20251031-rockchip-emmc-cqe-support-v2-2-958171f5edad@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+@@ -1935,6 +1935,7 @@
+ <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
+ <&cru SRST_T_EMMC>;
+ reset-names = "core", "bus", "axi", "block", "timer";
++ supports-cqe;
+ status = "disabled";
+ };
+
+++ /dev/null
-From 9d856aa1c81930a5d8df0e29d6cb0faa3fa87206 Mon Sep 17 00:00:00 2001
-From: Sebastian Reichel <sebastian.reichel@collabora.com>
-Date: Fri, 31 Oct 2025 16:58:24 +0100
-Subject: [PATCH] arm64: dts: rockchip: add eMMC CQE support for rk3588
-
-The RK3588 eMMC controller supports CQE, so add the missing
-DT flag.
-
-Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
-Link: https://patch.msgid.link/20251031-rockchip-emmc-cqe-support-v2-2-958171f5edad@collabora.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
-@@ -1935,6 +1935,7 @@
- <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
- <&cru SRST_T_EMMC>;
- reset-names = "core", "bus", "axi", "block", "timer";
-+ supports-cqe;
- status = "disabled";
- };
-
--- /dev/null
+From a2a18e5da64f8da306fa97c397b4c739ea776f37 Mon Sep 17 00:00:00 2001
+From: Shawn Lin <shawn.lin@rock-chips.com>
+Date: Tue, 18 Nov 2025 17:52:05 +0800
+Subject: [PATCH] phy: rockchip: naneng-combphy: Fix PCIe L1ss support RK3528
+
+When PCIe link enters L1 PM substates, the PHY will turn off its
+PLL for power-saving. However, it turns off the PLL too fast which
+leads the PHY to be broken. According to the PHY document, we need
+to delay PLL turnoff time.
+
+Fixes: bbcca4fac873 ("phy: rockchip: naneng-combphy: Add RK3528 support")
+Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
+Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
+Link: https://patch.msgid.link/1763459526-35004-1-git-send-email-shawn.lin@rock-chips.com
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+---
+ drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
++++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+@@ -21,6 +21,9 @@
+ #define REF_CLOCK_100MHz (100 * HZ_PER_MHZ)
+
+ /* RK3528 COMBO PHY REG */
++#define RK3528_PHYREG5 0x14
++#define RK3528_PHYREG5_GATE_TX_PCK_SEL BIT(3)
++#define RK3528_PHYREG5_GATE_TX_PCK_DLY_PLL_OFF BIT(3)
+ #define RK3528_PHYREG6 0x18
+ #define RK3528_PHYREG6_PLL_KVCO GENMASK(12, 10)
+ #define RK3528_PHYREG6_PLL_KVCO_VALUE 0x2
+@@ -504,6 +507,10 @@ static int rk3528_combphy_cfg(struct roc
+ case REF_CLOCK_100MHz:
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
+ if (priv->type == PHY_TYPE_PCIE) {
++ /* Gate_tx_pck_sel length select for L1ss support */
++ rockchip_combphy_updatel(priv, RK3528_PHYREG5_GATE_TX_PCK_SEL,
++ RK3528_PHYREG5_GATE_TX_PCK_DLY_PLL_OFF, RK3528_PHYREG5);
++
+ /* PLL KVCO tuning fine */
+ val = FIELD_PREP(RK3528_PHYREG6_PLL_KVCO, RK3528_PHYREG6_PLL_KVCO_VALUE);
+ rockchip_combphy_updatel(priv, RK3528_PHYREG6_PLL_KVCO, val,
+++ /dev/null
-From 7fee88882704a5ed7657f467ecb44e39b20f42aa Mon Sep 17 00:00:00 2001
-From: Tianling Shen <cnsztl@gmail.com>
-Date: Sat, 27 Sep 2025 17:23:10 +0800
-Subject: [PATCH] arm64: dts: rockchip: Add devicetree for the FriendlyElec
- NanoPi R76S
-
-The NanoPi R76S (as "R76S") is an open-sourced mini IoT gateway
-device with two 2.5G, designed and developed by FriendlyElec.
-
-Specification:
-- Rockchip RK3576
-- 2/4GB LPDDR4X RAM
-- 2x 2500Base-T (PCIe, rtl8125b)
-- 3x LEDs (Power, LAN, WAN)
-- 32GB eMMC
-- MicroSD Slot
-- MDMI 1.4/2.0 OUT
-- M.2 E-Key SDIO slot
-- USB 3.0 Port
-- USB Type-C 5V Power
-
-Signed-off-by: Tianling Shen <cnsztl@gmail.com>
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/Makefile | 1 +
- .../arm64/boot/dts/rockchip/rk3576-nanopi-r76s.dts | 860 +++++++++++++++++++++
- 2 files changed, 861 insertions(+)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3576-nanopi-r76s.dts
-
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -126,6 +126,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-ro
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-display-vz.dtbo
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-io-expander.dtbo
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-nanopi-r76s.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-rock-4d.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3582-radxa-e52c.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-armsom-sige7.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3576-nanopi-r76s.dts
-@@ -0,0 +1,860 @@
-+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-+/*
-+ * Copyright (c) 2025 FriendlyElec Computer Tech. Co., Ltd.
-+ * (http://www.friendlyelec.com)
-+ *
-+ * Copyright (c) 2025 Tianling Shen <cnsztl@gmail.com>
-+ */
-+
-+/dts-v1/;
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/input/input.h>
-+#include <dt-bindings/leds/common.h>
-+#include <dt-bindings/pinctrl/rockchip.h>
-+#include <dt-bindings/soc/rockchip,vop2.h>
-+
-+#include "rk3576.dtsi"
-+
-+/ {
-+ model = "FriendlyElec NanoPi R76S";
-+ compatible = "friendlyarm,nanopi-r76s", "rockchip,rk3576";
-+
-+ aliases {
-+ mmc0 = &sdhci;
-+ mmc1 = &sdmmc;
-+ mmc2 = &sdio;
-+ };
-+
-+ chosen {
-+ stdout-path = "serial0:1500000n8";
-+ };
-+
-+ gpio-keys {
-+ compatible = "gpio-keys";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&user_but_pin>;
-+
-+ button-reset {
-+ label = "reset";
-+ gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_LOW>;
-+ debounce-interval = <50>;
-+ linux,code = <KEY_RESTART>;
-+ wakeup-source;
-+ };
-+ };
-+
-+ gpio-leds {
-+ compatible = "gpio-leds";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&led1_h>, <&led_sys_h>, <&led2_h>;
-+
-+ led-0 {
-+ color = <LED_COLOR_ID_GREEN>;
-+ function = LED_FUNCTION_LAN;
-+ gpios = <&gpio2 RK_PB0 GPIO_ACTIVE_HIGH>;
-+ };
-+
-+ led-1 {
-+ color = <LED_COLOR_ID_RED>;
-+ function = LED_FUNCTION_POWER;
-+ gpios = <&gpio2 RK_PB3 GPIO_ACTIVE_HIGH>;
-+ linux,default-trigger = "heartbeat";
-+ };
-+
-+ led-2 {
-+ color = <LED_COLOR_ID_GREEN>;
-+ function = LED_FUNCTION_WAN;
-+ gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>;
-+ };
-+ };
-+
-+ hdmi-con {
-+ compatible = "hdmi-connector";
-+ hdmi-pwr-supply = <&vcc5v_hdmi_tx>;
-+ type = "a";
-+
-+ port {
-+ hdmi_con_in: endpoint {
-+ remote-endpoint = <&hdmi_out_con>;
-+ };
-+ };
-+ };
-+
-+ sdio_pwrseq: sdio-pwrseq {
-+ compatible = "mmc-pwrseq-simple";
-+ clocks = <&hym8563>;
-+ clock-names = "ext_clock";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&wifi_reg_on_h>;
-+ post-power-on-delay-ms = <200>;
-+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
-+ };
-+
-+ vcc3v3_rtc_s5: regulator-vcc3v3-rtc-s5 {
-+ compatible = "regulator-fixed";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-name = "vcc3v3_rtc_s5";
-+ vin-supply = <&vcc5v0_sys_s5>;
-+ };
-+
-+ vcc5v_dcin: regulator-vcc5v-dcin {
-+ compatible = "regulator-fixed";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ regulator-name = "vcc5v_dcin";
-+ };
-+
-+ vcc5v_hdmi_tx: regulator-vcc5v-hdmi-tx {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&hdmi_tx_on_h>;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ regulator-name = "vcc5v_hdmi_tx";
-+ vin-supply = <&vcc5v0_sys_s5>;
-+ };
-+
-+ vcc5v0_device_s0: regulator-vcc5v0-device-s0 {
-+ compatible = "regulator-fixed";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ regulator-name = "vcc5v0_device_s0";
-+ vin-supply = <&vcc5v_dcin>;
-+ };
-+
-+ vcc5v0_sys_s5: regulator-vcc5v0-sys-s5 {
-+ compatible = "regulator-fixed";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ regulator-name = "vcc5v0_sys_s5";
-+ vin-supply = <&vcc5v_dcin>;
-+ };
-+
-+ vcc5v0_usb_otg0: regulator-vcc5v0-usb-otg0 {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpios = <&gpio0 RK_PD1 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&usb_otg0_pwren_h>;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ regulator-name = "vcc5v0_usb_otg0";
-+ vin-supply = <&vcc5v0_sys_s5>;
-+ };
-+
-+ vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
-+ compatible = "regulator-fixed";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1100000>;
-+ regulator-max-microvolt = <1100000>;
-+ regulator-name = "vcc_1v1_nldo_s3";
-+ vin-supply = <&vcc5v0_sys_s5>;
-+ };
-+
-+ vcc_1v8_s0: regulator-vcc-1v8-s0 {
-+ compatible = "regulator-fixed";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ regulator-name = "vcc_1v8_s0";
-+ vin-supply = <&vcc_1v8_s3>;
-+ };
-+
-+ vcc_2v0_pldo_s3: regulator-vcc-2v0-pldo-s3 {
-+ compatible = "regulator-fixed";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <2000000>;
-+ regulator-max-microvolt = <2000000>;
-+ regulator-name = "vcc_2v0_pldo_s3";
-+ vin-supply = <&vcc5v0_sys_s5>;
-+ };
-+
-+ vcc_3v3_s0: regulator-vcc-3v3-s0 {
-+ compatible = "regulator-fixed";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-name = "vcc_3v3_s0";
-+ vin-supply = <&vcc_3v3_s3>;
-+ };
-+};
-+
-+&combphy0_ps {
-+ status = "okay";
-+};
-+
-+&combphy1_psu {
-+ status = "okay";
-+};
-+
-+&cpu_b0 {
-+ cpu-supply = <&vdd_cpu_big_s0>;
-+};
-+
-+&cpu_b1 {
-+ cpu-supply = <&vdd_cpu_big_s0>;
-+};
-+
-+&cpu_b2 {
-+ cpu-supply = <&vdd_cpu_big_s0>;
-+};
-+
-+&cpu_b3 {
-+ cpu-supply = <&vdd_cpu_big_s0>;
-+};
-+
-+&cpu_l0 {
-+ cpu-supply = <&vdd_cpu_lit_s0>;
-+};
-+
-+&cpu_l1 {
-+ cpu-supply = <&vdd_cpu_lit_s0>;
-+};
-+
-+&cpu_l2 {
-+ cpu-supply = <&vdd_cpu_lit_s0>;
-+};
-+
-+&cpu_l3 {
-+ cpu-supply = <&vdd_cpu_lit_s0>;
-+};
-+
-+&gpu {
-+ mali-supply = <&vdd_gpu_s0>;
-+ status = "okay";
-+};
-+
-+&hdmi {
-+ status = "okay";
-+};
-+
-+&hdmi_in {
-+ hdmi_in_vp0: endpoint {
-+ remote-endpoint = <&vp0_out_hdmi>;
-+ };
-+};
-+
-+&hdmi_out {
-+ hdmi_out_con: endpoint {
-+ remote-endpoint = <&hdmi_con_in>;
-+ };
-+};
-+
-+&hdmi_sound {
-+ status = "okay";
-+};
-+
-+&hdptxphy {
-+ status = "okay";
-+};
-+
-+&i2c1 {
-+ status = "okay";
-+
-+ pmic@23 {
-+ compatible = "rockchip,rk806";
-+ reg = <0x23>;
-+ #gpio-cells = <2>;
-+ gpio-controller;
-+ interrupt-parent = <&gpio0>;
-+ interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
-+ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
-+ system-power-controller;
-+
-+ vcc1-supply = <&vcc5v0_sys_s5>;
-+ vcc2-supply = <&vcc5v0_sys_s5>;
-+ vcc3-supply = <&vcc5v0_sys_s5>;
-+ vcc4-supply = <&vcc5v0_sys_s5>;
-+ vcc5-supply = <&vcc5v0_sys_s5>;
-+ vcc6-supply = <&vcc5v0_sys_s5>;
-+ vcc7-supply = <&vcc5v0_sys_s5>;
-+ vcc8-supply = <&vcc5v0_sys_s5>;
-+ vcc9-supply = <&vcc5v0_sys_s5>;
-+ vcc10-supply = <&vcc5v0_sys_s5>;
-+ vcc11-supply = <&vcc_2v0_pldo_s3>;
-+ vcc12-supply = <&vcc5v0_sys_s5>;
-+ vcc13-supply = <&vcc_1v1_nldo_s3>;
-+ vcc14-supply = <&vcc_1v1_nldo_s3>;
-+ vcca-supply = <&vcc5v0_sys_s5>;
-+
-+ rk806_dvs1_null: dvs1-null-pins {
-+ pins = "gpio_pwrctrl1";
-+ function = "pin_fun0";
-+ };
-+
-+ rk806_dvs1_pwrdn: dvs1-pwrdn-pins {
-+ pins = "gpio_pwrctrl1";
-+ function = "pin_fun2";
-+ };
-+
-+ rk806_dvs1_rst: dvs1-rst-pins {
-+ pins = "gpio_pwrctrl1";
-+ function = "pin_fun3";
-+ };
-+
-+ rk806_dvs1_slp: dvs1-slp-pins {
-+ pins = "gpio_pwrctrl1";
-+ function = "pin_fun1";
-+ };
-+
-+ rk806_dvs2_dvs: dvs2-dvs-pins {
-+ pins = "gpio_pwrctrl2";
-+ function = "pin_fun4";
-+ };
-+
-+ rk806_dvs2_gpio: dvs2-gpio-pins {
-+ pins = "gpio_pwrctrl2";
-+ function = "pin_fun5";
-+ };
-+
-+ rk806_dvs2_null: dvs2-null-pins {
-+ pins = "gpio_pwrctrl2";
-+ function = "pin_fun0";
-+ };
-+
-+ rk806_dvs2_pwrdn: dvs2-pwrdn-pins {
-+ pins = "gpio_pwrctrl2";
-+ function = "pin_fun2";
-+ };
-+
-+ rk806_dvs2_rst: dvs2-rst-pins {
-+ pins = "gpio_pwrctrl2";
-+ function = "pin_fun3";
-+ };
-+
-+ rk806_dvs2_slp: dvs2-slp-pins {
-+ pins = "gpio_pwrctrl2";
-+ function = "pin_fun1";
-+ };
-+
-+ rk806_dvs3_dvs: dvs3-dvs-pins {
-+ pins = "gpio_pwrctrl3";
-+ function = "pin_fun4";
-+ };
-+
-+ rk806_dvs3_gpio: dvs3-gpio-pins {
-+ pins = "gpio_pwrctrl3";
-+ function = "pin_fun5";
-+ };
-+
-+ rk806_dvs3_null: dvs3-null-pins {
-+ pins = "gpio_pwrctrl3";
-+ function = "pin_fun0";
-+ };
-+
-+ rk806_dvs3_pwrdn: dvs3-pwrdn-pins {
-+ pins = "gpio_pwrctrl3";
-+ function = "pin_fun2";
-+ };
-+
-+ rk806_dvs3_rst: dvs3-rst-pins {
-+ pins = "gpio_pwrctrl3";
-+ function = "pin_fun3";
-+ };
-+
-+ rk806_dvs3_slp: dvs3-slp-pins {
-+ pins = "gpio_pwrctrl3";
-+ function = "pin_fun1";
-+ };
-+
-+ regulators {
-+ vdd_cpu_big_s0: dcdc-reg1 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-enable-ramp-delay = <400>;
-+ regulator-min-microvolt = <550000>;
-+ regulator-max-microvolt = <950000>;
-+ regulator-name = "vdd_cpu_big_s0";
-+ regulator-ramp-delay = <12500>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdd_npu_s0: dcdc-reg2 {
-+ regulator-boot-on;
-+ regulator-enable-ramp-delay = <400>;
-+ regulator-min-microvolt = <550000>;
-+ regulator-max-microvolt = <950000>;
-+ regulator-name = "vdd_npu_s0";
-+ regulator-ramp-delay = <12500>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdd_cpu_lit_s0: dcdc-reg3 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <550000>;
-+ regulator-max-microvolt = <950000>;
-+ regulator-name = "vdd_cpu_lit_s0";
-+ regulator-ramp-delay = <12500>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ regulator-suspend-microvolt = <750000>;
-+ };
-+ };
-+
-+ vcc_3v3_s3: dcdc-reg4 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-name = "vcc_3v3_s3";
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <3300000>;
-+ };
-+ };
-+
-+ vdd_gpu_s0: dcdc-reg5 {
-+ regulator-boot-on;
-+ regulator-enable-ramp-delay = <400>;
-+ regulator-min-microvolt = <550000>;
-+ regulator-max-microvolt = <900000>;
-+ regulator-name = "vdd_gpu_s0";
-+ regulator-ramp-delay = <12500>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ regulator-suspend-microvolt = <850000>;
-+ };
-+ };
-+
-+ vddq_ddr_s0: dcdc-reg6 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-name = "vddq_ddr_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdd_logic_s0: dcdc-reg7 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <550000>;
-+ regulator-max-microvolt = <800000>;
-+ regulator-name = "vdd_logic_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc_1v8_s3: dcdc-reg8 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ regulator-name = "vcc_1v8_s3";
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <1800000>;
-+ };
-+ };
-+
-+ vdd2_ddr_s3: dcdc-reg9 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-name = "vdd2_ddr_s3";
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ };
-+ };
-+
-+ vdd_ddr_s0: dcdc-reg10 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <550000>;
-+ regulator-max-microvolt = <1200000>;
-+ regulator-name = "vdd_ddr_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcca_1v8_s0: pldo-reg1 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ regulator-name = "vcca_1v8_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcca1v8_pldo2_s0: pldo-reg2 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ regulator-name = "vcca1v8_pldo2_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdda_1v2_s0: pldo-reg3 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1200000>;
-+ regulator-max-microvolt = <1200000>;
-+ regulator-name = "vdda_1v2_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcca_3v3_s0: pldo-reg4 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-name = "vcca_3v3_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vccio_sd_s0: pldo-reg5 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-name = "vccio_sd_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcca1v8_pldo6_s3: pldo-reg6 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ regulator-name = "vcca1v8_pldo6_s3";
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <1800000>;
-+ };
-+ };
-+
-+ vdd_0v75_s3: nldo-reg1 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <750000>;
-+ regulator-max-microvolt = <750000>;
-+ regulator-name = "vdd_0v75_s3";
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <750000>;
-+ };
-+ };
-+
-+ vdda_ddr_pll_s0: nldo-reg2 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <850000>;
-+ regulator-max-microvolt = <850000>;
-+ regulator-name = "vdda_ddr_pll_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdda0v75_hdmi_s0: nldo-reg3 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <837500>;
-+ regulator-max-microvolt = <837500>;
-+ regulator-name = "vdda0v75_hdmi_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdda_0v85_s0: nldo-reg4 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <850000>;
-+ regulator-max-microvolt = <850000>;
-+ regulator-name = "vdda_0v85_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdda_0v75_s0: nldo-reg5 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <750000>;
-+ regulator-max-microvolt = <750000>;
-+ regulator-name = "vdda_0v75_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+ };
-+ };
-+};
-+
-+&i2c2 {
-+ status = "okay";
-+
-+ hym8563: rtc@51 {
-+ compatible = "haoyu,hym8563";
-+ reg = <0x51>;
-+ #clock-cells = <0>;
-+ clock-output-names = "hym8563";
-+ interrupt-parent = <&gpio0>;
-+ interrupts = <RK_PA5 IRQ_TYPE_LEVEL_LOW>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&rtc_int_l>;
-+ wakeup-source;
-+ };
-+};
-+
-+&pcie0 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pcie0_perstn>;
-+ reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
-+ vpcie3v3-supply = <&vcc_3v3_s3>;
-+ status = "okay";
-+};
-+
-+&pcie1 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pcie1_perstn>;
-+ reset-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
-+ vpcie3v3-supply = <&vcc_3v3_s3>;
-+ status = "okay";
-+};
-+
-+&pinctrl {
-+ bt {
-+ bt_reg_on_h: bt-reg-on-h {
-+ rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
-+ };
-+
-+ bt_wake_host_h: bt-wake-host-h {
-+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>;
-+ };
-+
-+ host_wake_bt_h: host-wake-bt-h {
-+ rockchip,pins = <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
-+ };
-+ };
-+
-+ gpio-keys {
-+ user_but_pin: user-but-pin {
-+ rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
-+ };
-+ };
-+
-+ gpio-leds {
-+ led_sys_h: led-sys-h {
-+ rockchip,pins = <2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ led1_h: led1-h {
-+ rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ led2_h: led2-h {
-+ rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ hdmi {
-+ hdmi_tx_on_h: hdmi-tx-on-h {
-+ rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ hym8563 {
-+ rtc_int_l: rtc-int-l {
-+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
-+ };
-+ };
-+
-+ pcie {
-+ pcie0_perstn: pcie0-perstn {
-+ rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
-+ };
-+
-+ pcie1_perstn: pcie1-perstn {
-+ rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
-+ };
-+ };
-+
-+ usb {
-+ usb_otg0_pwren_h: usb-otg0-pwren-h {
-+ rockchip,pins = <0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ wifi {
-+ wifi_wake_host_h: wifi-wake-host-h {
-+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>;
-+ };
-+
-+ wifi_reg_on_h: wifi-reg-on-h {
-+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+};
-+
-+&sai6 {
-+ status = "okay";
-+};
-+
-+&sdmmc {
-+ bus-width = <4>;
-+ cap-mmc-highspeed;
-+ cap-sd-highspeed;
-+ disable-wp;
-+ no-mmc;
-+ no-sdio;
-+ sd-uhs-sdr104;
-+ vmmc-supply = <&vcc_3v3_s3>;
-+ vqmmc-supply = <&vccio_sd_s0>;
-+ status = "okay";
-+};
-+
-+&sdio {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ bus-width = <4>;
-+ cap-sd-highspeed;
-+ cap-sdio-irq;
-+ disable-wp;
-+ keep-power-in-suspend;
-+ mmc-pwrseq = <&sdio_pwrseq>;
-+ no-mmc;
-+ no-sd;
-+ non-removable;
-+ sd-uhs-sdr104;
-+ vmmc-supply = <&vcc_3v3_s3>;
-+ vqmmc-supply = <&vcc_1v8_s3>;
-+ wakeup-source;
-+ status = "okay";
-+
-+ rtl8822cs: wifi@1 {
-+ reg = <1>;
-+ interrupt-parent = <&gpio0>;
-+ interrupts = <RK_PB0 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "host-wake";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&wifi_wake_host_h>;
-+ };
-+};
-+
-+&sdhci {
-+ bus-width = <8>;
-+ cap-mmc-highspeed;
-+ full-pwr-cycle-in-suspend;
-+ mmc-hs400-1_8v;
-+ mmc-hs400-enhanced-strobe;
-+ no-sdio;
-+ no-sd;
-+ non-removable;
-+ status = "okay";
-+};
-+
-+&saradc {
-+ vref-supply = <&vcca_1v8_s0>;
-+ status = "okay";
-+};
-+
-+&u2phy0 {
-+ status = "okay";
-+};
-+
-+&u2phy0_otg {
-+ phy-supply = <&vcc5v0_usb_otg0>;
-+ status = "okay";
-+};
-+
-+&uart0 {
-+ status = "okay";
-+};
-+
-+&uart5 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&uart5m0_xfer &uart5m0_ctsn &uart5m0_rtsn>;
-+ uart-has-rtscts;
-+ status = "okay";
-+
-+ bluetooth {
-+ compatible = "realtek,rtl8822cs-bt";
-+ enable-gpios = <&gpio3 RK_PC7 GPIO_ACTIVE_HIGH>;
-+ device-wake-gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_HIGH>;
-+ host-wake-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&bt_wake_host_h &host_wake_bt_h &bt_reg_on_h>;
-+ };
-+};
-+
-+&usbdp_phy {
-+ status = "okay";
-+};
-+
-+&usb_drd0_dwc3 {
-+ dr_mode = "host";
-+ extcon = <&u2phy0>;
-+ status = "okay";
-+};
-+
-+&vop {
-+ status = "okay";
-+};
-+
-+&vop_mmu {
-+ status = "okay";
-+};
-+
-+&vp0 {
-+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
-+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
-+ remote-endpoint = <&hdmi_in_vp0>;
-+ };
-+};
--- /dev/null
+From 7fee88882704a5ed7657f467ecb44e39b20f42aa Mon Sep 17 00:00:00 2001
+From: Tianling Shen <cnsztl@gmail.com>
+Date: Sat, 27 Sep 2025 17:23:10 +0800
+Subject: [PATCH] arm64: dts: rockchip: Add devicetree for the FriendlyElec
+ NanoPi R76S
+
+The NanoPi R76S (as "R76S") is an open-sourced mini IoT gateway
+device with two 2.5G, designed and developed by FriendlyElec.
+
+Specification:
+- Rockchip RK3576
+- 2/4GB LPDDR4X RAM
+- 2x 2500Base-T (PCIe, rtl8125b)
+- 3x LEDs (Power, LAN, WAN)
+- 32GB eMMC
+- MicroSD Slot
+- MDMI 1.4/2.0 OUT
+- M.2 E-Key SDIO slot
+- USB 3.0 Port
+- USB Type-C 5V Power
+
+Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/Makefile | 1 +
+ .../arm64/boot/dts/rockchip/rk3576-nanopi-r76s.dts | 860 +++++++++++++++++++++
+ 2 files changed, 861 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3576-nanopi-r76s.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -126,6 +126,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-ro
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-display-vz.dtbo
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-io-expander.dtbo
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-nanopi-r76s.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-rock-4d.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3582-radxa-e52c.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-armsom-sige7.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3576-nanopi-r76s.dts
+@@ -0,0 +1,860 @@
++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
++/*
++ * Copyright (c) 2025 FriendlyElec Computer Tech. Co., Ltd.
++ * (http://www.friendlyelec.com)
++ *
++ * Copyright (c) 2025 Tianling Shen <cnsztl@gmail.com>
++ */
++
++/dts-v1/;
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/leds/common.h>
++#include <dt-bindings/pinctrl/rockchip.h>
++#include <dt-bindings/soc/rockchip,vop2.h>
++
++#include "rk3576.dtsi"
++
++/ {
++ model = "FriendlyElec NanoPi R76S";
++ compatible = "friendlyarm,nanopi-r76s", "rockchip,rk3576";
++
++ aliases {
++ mmc0 = &sdhci;
++ mmc1 = &sdmmc;
++ mmc2 = &sdio;
++ };
++
++ chosen {
++ stdout-path = "serial0:1500000n8";
++ };
++
++ gpio-keys {
++ compatible = "gpio-keys";
++ pinctrl-names = "default";
++ pinctrl-0 = <&user_but_pin>;
++
++ button-reset {
++ label = "reset";
++ gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_LOW>;
++ debounce-interval = <50>;
++ linux,code = <KEY_RESTART>;
++ wakeup-source;
++ };
++ };
++
++ gpio-leds {
++ compatible = "gpio-leds";
++ pinctrl-names = "default";
++ pinctrl-0 = <&led1_h>, <&led_sys_h>, <&led2_h>;
++
++ led-0 {
++ color = <LED_COLOR_ID_GREEN>;
++ function = LED_FUNCTION_LAN;
++ gpios = <&gpio2 RK_PB0 GPIO_ACTIVE_HIGH>;
++ };
++
++ led-1 {
++ color = <LED_COLOR_ID_RED>;
++ function = LED_FUNCTION_POWER;
++ gpios = <&gpio2 RK_PB3 GPIO_ACTIVE_HIGH>;
++ linux,default-trigger = "heartbeat";
++ };
++
++ led-2 {
++ color = <LED_COLOR_ID_GREEN>;
++ function = LED_FUNCTION_WAN;
++ gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>;
++ };
++ };
++
++ hdmi-con {
++ compatible = "hdmi-connector";
++ hdmi-pwr-supply = <&vcc5v_hdmi_tx>;
++ type = "a";
++
++ port {
++ hdmi_con_in: endpoint {
++ remote-endpoint = <&hdmi_out_con>;
++ };
++ };
++ };
++
++ sdio_pwrseq: sdio-pwrseq {
++ compatible = "mmc-pwrseq-simple";
++ clocks = <&hym8563>;
++ clock-names = "ext_clock";
++ pinctrl-names = "default";
++ pinctrl-0 = <&wifi_reg_on_h>;
++ post-power-on-delay-ms = <200>;
++ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
++ };
++
++ vcc3v3_rtc_s5: regulator-vcc3v3-rtc-s5 {
++ compatible = "regulator-fixed";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-name = "vcc3v3_rtc_s5";
++ vin-supply = <&vcc5v0_sys_s5>;
++ };
++
++ vcc5v_dcin: regulator-vcc5v-dcin {
++ compatible = "regulator-fixed";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ regulator-name = "vcc5v_dcin";
++ };
++
++ vcc5v_hdmi_tx: regulator-vcc5v-hdmi-tx {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&hdmi_tx_on_h>;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ regulator-name = "vcc5v_hdmi_tx";
++ vin-supply = <&vcc5v0_sys_s5>;
++ };
++
++ vcc5v0_device_s0: regulator-vcc5v0-device-s0 {
++ compatible = "regulator-fixed";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ regulator-name = "vcc5v0_device_s0";
++ vin-supply = <&vcc5v_dcin>;
++ };
++
++ vcc5v0_sys_s5: regulator-vcc5v0-sys-s5 {
++ compatible = "regulator-fixed";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ regulator-name = "vcc5v0_sys_s5";
++ vin-supply = <&vcc5v_dcin>;
++ };
++
++ vcc5v0_usb_otg0: regulator-vcc5v0-usb-otg0 {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpios = <&gpio0 RK_PD1 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&usb_otg0_pwren_h>;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ regulator-name = "vcc5v0_usb_otg0";
++ vin-supply = <&vcc5v0_sys_s5>;
++ };
++
++ vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
++ compatible = "regulator-fixed";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1100000>;
++ regulator-max-microvolt = <1100000>;
++ regulator-name = "vcc_1v1_nldo_s3";
++ vin-supply = <&vcc5v0_sys_s5>;
++ };
++
++ vcc_1v8_s0: regulator-vcc-1v8-s0 {
++ compatible = "regulator-fixed";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-name = "vcc_1v8_s0";
++ vin-supply = <&vcc_1v8_s3>;
++ };
++
++ vcc_2v0_pldo_s3: regulator-vcc-2v0-pldo-s3 {
++ compatible = "regulator-fixed";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <2000000>;
++ regulator-max-microvolt = <2000000>;
++ regulator-name = "vcc_2v0_pldo_s3";
++ vin-supply = <&vcc5v0_sys_s5>;
++ };
++
++ vcc_3v3_s0: regulator-vcc-3v3-s0 {
++ compatible = "regulator-fixed";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-name = "vcc_3v3_s0";
++ vin-supply = <&vcc_3v3_s3>;
++ };
++};
++
++&combphy0_ps {
++ status = "okay";
++};
++
++&combphy1_psu {
++ status = "okay";
++};
++
++&cpu_b0 {
++ cpu-supply = <&vdd_cpu_big_s0>;
++};
++
++&cpu_b1 {
++ cpu-supply = <&vdd_cpu_big_s0>;
++};
++
++&cpu_b2 {
++ cpu-supply = <&vdd_cpu_big_s0>;
++};
++
++&cpu_b3 {
++ cpu-supply = <&vdd_cpu_big_s0>;
++};
++
++&cpu_l0 {
++ cpu-supply = <&vdd_cpu_lit_s0>;
++};
++
++&cpu_l1 {
++ cpu-supply = <&vdd_cpu_lit_s0>;
++};
++
++&cpu_l2 {
++ cpu-supply = <&vdd_cpu_lit_s0>;
++};
++
++&cpu_l3 {
++ cpu-supply = <&vdd_cpu_lit_s0>;
++};
++
++&gpu {
++ mali-supply = <&vdd_gpu_s0>;
++ status = "okay";
++};
++
++&hdmi {
++ status = "okay";
++};
++
++&hdmi_in {
++ hdmi_in_vp0: endpoint {
++ remote-endpoint = <&vp0_out_hdmi>;
++ };
++};
++
++&hdmi_out {
++ hdmi_out_con: endpoint {
++ remote-endpoint = <&hdmi_con_in>;
++ };
++};
++
++&hdmi_sound {
++ status = "okay";
++};
++
++&hdptxphy {
++ status = "okay";
++};
++
++&i2c1 {
++ status = "okay";
++
++ pmic@23 {
++ compatible = "rockchip,rk806";
++ reg = <0x23>;
++ #gpio-cells = <2>;
++ gpio-controller;
++ interrupt-parent = <&gpio0>;
++ interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
++ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
++ system-power-controller;
++
++ vcc1-supply = <&vcc5v0_sys_s5>;
++ vcc2-supply = <&vcc5v0_sys_s5>;
++ vcc3-supply = <&vcc5v0_sys_s5>;
++ vcc4-supply = <&vcc5v0_sys_s5>;
++ vcc5-supply = <&vcc5v0_sys_s5>;
++ vcc6-supply = <&vcc5v0_sys_s5>;
++ vcc7-supply = <&vcc5v0_sys_s5>;
++ vcc8-supply = <&vcc5v0_sys_s5>;
++ vcc9-supply = <&vcc5v0_sys_s5>;
++ vcc10-supply = <&vcc5v0_sys_s5>;
++ vcc11-supply = <&vcc_2v0_pldo_s3>;
++ vcc12-supply = <&vcc5v0_sys_s5>;
++ vcc13-supply = <&vcc_1v1_nldo_s3>;
++ vcc14-supply = <&vcc_1v1_nldo_s3>;
++ vcca-supply = <&vcc5v0_sys_s5>;
++
++ rk806_dvs1_null: dvs1-null-pins {
++ pins = "gpio_pwrctrl1";
++ function = "pin_fun0";
++ };
++
++ rk806_dvs1_pwrdn: dvs1-pwrdn-pins {
++ pins = "gpio_pwrctrl1";
++ function = "pin_fun2";
++ };
++
++ rk806_dvs1_rst: dvs1-rst-pins {
++ pins = "gpio_pwrctrl1";
++ function = "pin_fun3";
++ };
++
++ rk806_dvs1_slp: dvs1-slp-pins {
++ pins = "gpio_pwrctrl1";
++ function = "pin_fun1";
++ };
++
++ rk806_dvs2_dvs: dvs2-dvs-pins {
++ pins = "gpio_pwrctrl2";
++ function = "pin_fun4";
++ };
++
++ rk806_dvs2_gpio: dvs2-gpio-pins {
++ pins = "gpio_pwrctrl2";
++ function = "pin_fun5";
++ };
++
++ rk806_dvs2_null: dvs2-null-pins {
++ pins = "gpio_pwrctrl2";
++ function = "pin_fun0";
++ };
++
++ rk806_dvs2_pwrdn: dvs2-pwrdn-pins {
++ pins = "gpio_pwrctrl2";
++ function = "pin_fun2";
++ };
++
++ rk806_dvs2_rst: dvs2-rst-pins {
++ pins = "gpio_pwrctrl2";
++ function = "pin_fun3";
++ };
++
++ rk806_dvs2_slp: dvs2-slp-pins {
++ pins = "gpio_pwrctrl2";
++ function = "pin_fun1";
++ };
++
++ rk806_dvs3_dvs: dvs3-dvs-pins {
++ pins = "gpio_pwrctrl3";
++ function = "pin_fun4";
++ };
++
++ rk806_dvs3_gpio: dvs3-gpio-pins {
++ pins = "gpio_pwrctrl3";
++ function = "pin_fun5";
++ };
++
++ rk806_dvs3_null: dvs3-null-pins {
++ pins = "gpio_pwrctrl3";
++ function = "pin_fun0";
++ };
++
++ rk806_dvs3_pwrdn: dvs3-pwrdn-pins {
++ pins = "gpio_pwrctrl3";
++ function = "pin_fun2";
++ };
++
++ rk806_dvs3_rst: dvs3-rst-pins {
++ pins = "gpio_pwrctrl3";
++ function = "pin_fun3";
++ };
++
++ rk806_dvs3_slp: dvs3-slp-pins {
++ pins = "gpio_pwrctrl3";
++ function = "pin_fun1";
++ };
++
++ regulators {
++ vdd_cpu_big_s0: dcdc-reg1 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-enable-ramp-delay = <400>;
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <950000>;
++ regulator-name = "vdd_cpu_big_s0";
++ regulator-ramp-delay = <12500>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdd_npu_s0: dcdc-reg2 {
++ regulator-boot-on;
++ regulator-enable-ramp-delay = <400>;
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <950000>;
++ regulator-name = "vdd_npu_s0";
++ regulator-ramp-delay = <12500>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdd_cpu_lit_s0: dcdc-reg3 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <950000>;
++ regulator-name = "vdd_cpu_lit_s0";
++ regulator-ramp-delay = <12500>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ regulator-suspend-microvolt = <750000>;
++ };
++ };
++
++ vcc_3v3_s3: dcdc-reg4 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-name = "vcc_3v3_s3";
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <3300000>;
++ };
++ };
++
++ vdd_gpu_s0: dcdc-reg5 {
++ regulator-boot-on;
++ regulator-enable-ramp-delay = <400>;
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <900000>;
++ regulator-name = "vdd_gpu_s0";
++ regulator-ramp-delay = <12500>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ regulator-suspend-microvolt = <850000>;
++ };
++ };
++
++ vddq_ddr_s0: dcdc-reg6 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-name = "vddq_ddr_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdd_logic_s0: dcdc-reg7 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <800000>;
++ regulator-name = "vdd_logic_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcc_1v8_s3: dcdc-reg8 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-name = "vcc_1v8_s3";
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1800000>;
++ };
++ };
++
++ vdd2_ddr_s3: dcdc-reg9 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-name = "vdd2_ddr_s3";
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ };
++ };
++
++ vdd_ddr_s0: dcdc-reg10 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <1200000>;
++ regulator-name = "vdd_ddr_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcca_1v8_s0: pldo-reg1 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-name = "vcca_1v8_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcca1v8_pldo2_s0: pldo-reg2 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-name = "vcca1v8_pldo2_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdda_1v2_s0: pldo-reg3 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1200000>;
++ regulator-max-microvolt = <1200000>;
++ regulator-name = "vdda_1v2_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcca_3v3_s0: pldo-reg4 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-name = "vcca_3v3_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vccio_sd_s0: pldo-reg5 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-name = "vccio_sd_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcca1v8_pldo6_s3: pldo-reg6 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-name = "vcca1v8_pldo6_s3";
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1800000>;
++ };
++ };
++
++ vdd_0v75_s3: nldo-reg1 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <750000>;
++ regulator-max-microvolt = <750000>;
++ regulator-name = "vdd_0v75_s3";
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <750000>;
++ };
++ };
++
++ vdda_ddr_pll_s0: nldo-reg2 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <850000>;
++ regulator-max-microvolt = <850000>;
++ regulator-name = "vdda_ddr_pll_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdda0v75_hdmi_s0: nldo-reg3 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <837500>;
++ regulator-max-microvolt = <837500>;
++ regulator-name = "vdda0v75_hdmi_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdda_0v85_s0: nldo-reg4 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <850000>;
++ regulator-max-microvolt = <850000>;
++ regulator-name = "vdda_0v85_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdda_0v75_s0: nldo-reg5 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <750000>;
++ regulator-max-microvolt = <750000>;
++ regulator-name = "vdda_0v75_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++ };
++ };
++};
++
++&i2c2 {
++ status = "okay";
++
++ hym8563: rtc@51 {
++ compatible = "haoyu,hym8563";
++ reg = <0x51>;
++ #clock-cells = <0>;
++ clock-output-names = "hym8563";
++ interrupt-parent = <&gpio0>;
++ interrupts = <RK_PA5 IRQ_TYPE_LEVEL_LOW>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&rtc_int_l>;
++ wakeup-source;
++ };
++};
++
++&pcie0 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pcie0_perstn>;
++ reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
++ vpcie3v3-supply = <&vcc_3v3_s3>;
++ status = "okay";
++};
++
++&pcie1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pcie1_perstn>;
++ reset-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
++ vpcie3v3-supply = <&vcc_3v3_s3>;
++ status = "okay";
++};
++
++&pinctrl {
++ bt {
++ bt_reg_on_h: bt-reg-on-h {
++ rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++
++ bt_wake_host_h: bt-wake-host-h {
++ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>;
++ };
++
++ host_wake_bt_h: host-wake-bt-h {
++ rockchip,pins = <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++ };
++
++ gpio-keys {
++ user_but_pin: user-but-pin {
++ rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++ };
++
++ gpio-leds {
++ led_sys_h: led-sys-h {
++ rockchip,pins = <2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ led1_h: led1-h {
++ rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ led2_h: led2-h {
++ rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ hdmi {
++ hdmi_tx_on_h: hdmi-tx-on-h {
++ rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ hym8563 {
++ rtc_int_l: rtc-int-l {
++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++ };
++
++ pcie {
++ pcie0_perstn: pcie0-perstn {
++ rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++
++ pcie1_perstn: pcie1-perstn {
++ rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++ };
++
++ usb {
++ usb_otg0_pwren_h: usb-otg0-pwren-h {
++ rockchip,pins = <0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ wifi {
++ wifi_wake_host_h: wifi-wake-host-h {
++ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>;
++ };
++
++ wifi_reg_on_h: wifi-reg-on-h {
++ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++};
++
++&sai6 {
++ status = "okay";
++};
++
++&sdmmc {
++ bus-width = <4>;
++ cap-mmc-highspeed;
++ cap-sd-highspeed;
++ disable-wp;
++ no-mmc;
++ no-sdio;
++ sd-uhs-sdr104;
++ vmmc-supply = <&vcc_3v3_s3>;
++ vqmmc-supply = <&vccio_sd_s0>;
++ status = "okay";
++};
++
++&sdio {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ bus-width = <4>;
++ cap-sd-highspeed;
++ cap-sdio-irq;
++ disable-wp;
++ keep-power-in-suspend;
++ mmc-pwrseq = <&sdio_pwrseq>;
++ no-mmc;
++ no-sd;
++ non-removable;
++ sd-uhs-sdr104;
++ vmmc-supply = <&vcc_3v3_s3>;
++ vqmmc-supply = <&vcc_1v8_s3>;
++ wakeup-source;
++ status = "okay";
++
++ rtl8822cs: wifi@1 {
++ reg = <1>;
++ interrupt-parent = <&gpio0>;
++ interrupts = <RK_PB0 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "host-wake";
++ pinctrl-names = "default";
++ pinctrl-0 = <&wifi_wake_host_h>;
++ };
++};
++
++&sdhci {
++ bus-width = <8>;
++ cap-mmc-highspeed;
++ full-pwr-cycle-in-suspend;
++ mmc-hs400-1_8v;
++ mmc-hs400-enhanced-strobe;
++ no-sdio;
++ no-sd;
++ non-removable;
++ status = "okay";
++};
++
++&saradc {
++ vref-supply = <&vcca_1v8_s0>;
++ status = "okay";
++};
++
++&u2phy0 {
++ status = "okay";
++};
++
++&u2phy0_otg {
++ phy-supply = <&vcc5v0_usb_otg0>;
++ status = "okay";
++};
++
++&uart0 {
++ status = "okay";
++};
++
++&uart5 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&uart5m0_xfer &uart5m0_ctsn &uart5m0_rtsn>;
++ uart-has-rtscts;
++ status = "okay";
++
++ bluetooth {
++ compatible = "realtek,rtl8822cs-bt";
++ enable-gpios = <&gpio3 RK_PC7 GPIO_ACTIVE_HIGH>;
++ device-wake-gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_HIGH>;
++ host-wake-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&bt_wake_host_h &host_wake_bt_h &bt_reg_on_h>;
++ };
++};
++
++&usbdp_phy {
++ status = "okay";
++};
++
++&usb_drd0_dwc3 {
++ dr_mode = "host";
++ extcon = <&u2phy0>;
++ status = "okay";
++};
++
++&vop {
++ status = "okay";
++};
++
++&vop_mmu {
++ status = "okay";
++};
++
++&vp0 {
++ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
++ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
++ remote-endpoint = <&hdmi_in_vp0>;
++ };
++};
+++ /dev/null
-From 263fac6b09b42a1b077c21354370d38758237ab0 Mon Sep 17 00:00:00 2001
-From: Yao Zi <ziyao@disroot.org>
-Date: Thu, 18 Sep 2025 15:30:56 +0000
-Subject: [PATCH] arm64: dts: rockchip: Add PCIe Gen2x1 controller for RK3528
-
-Describes the PCIe Gen2x1 controller integrated in RK3528 SoC. The SoC
-doesn't provide a separate MSI controller, thus the one integrated in
-designware PCIe IP must be used.
-
-Signed-off-by: Yao Zi <ziyao@disroot.org>
-Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
-Link: https://patch.msgid.link/20250918153057.56023-3-ziyao@disroot.org
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3528.dtsi | 56 +++++++++++++++++++++++++++++++-
- 1 file changed, 55 insertions(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
-@@ -7,6 +7,7 @@
- #include <dt-bindings/gpio/gpio.h>
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/interrupt-controller/irq.h>
-+#include <dt-bindings/phy/phy.h>
- #include <dt-bindings/pinctrl/rockchip.h>
- #include <dt-bindings/clock/rockchip,rk3528-cru.h>
- #include <dt-bindings/power/rockchip,rk3528-power.h>
-@@ -294,10 +295,63 @@
-
- soc {
- compatible = "simple-bus";
-- ranges = <0x0 0xfe000000 0x0 0xfe000000 0x0 0x2000000>;
-+ ranges = <0x0 0xfc000000 0x0 0xfc000000 0x0 0x44000000>;
- #address-cells = <2>;
- #size-cells = <2>;
-
-+ pcie: pcie@fe000000 {
-+ compatible = "rockchip,rk3528-pcie",
-+ "rockchip,rk3568-pcie";
-+ reg = <0x0 0xfe000000 0x0 0x400000>,
-+ <0x0 0xfe4f0000 0x0 0x010000>,
-+ <0x0 0xfc000000 0x0 0x100000>;
-+ reg-names = "dbi", "apb", "config";
-+ bus-range = <0x0 0xff>;
-+ clocks = <&cru ACLK_PCIE>, <&cru HCLK_PCIE_SLV>,
-+ <&cru HCLK_PCIE_DBI>, <&cru PCLK_PCIE>,
-+ <&cru CLK_PCIE_AUX>;
-+ clock-names = "aclk_mst", "aclk_slv",
-+ "aclk_dbi", "pclk",
-+ "aux";
-+ device_type = "pci";
-+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "sys", "pmc", "msg", "legacy", "err",
-+ "msi";
-+ #interrupt-cells = <1>;
-+ interrupt-map-mask = <0 0 0 7>;
-+ interrupt-map = <0 0 0 1 &pcie_intc 0>,
-+ <0 0 0 2 &pcie_intc 1>,
-+ <0 0 0 3 &pcie_intc 2>,
-+ <0 0 0 4 &pcie_intc 3>;
-+ linux,pci-domain = <0>;
-+ max-link-speed = <2>;
-+ num-lanes = <1>;
-+ phys = <&combphy PHY_TYPE_PCIE>;
-+ phy-names = "pcie-phy";
-+ power-domains = <&power RK3528_PD_VPU>;
-+ ranges = <0x01000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x00100000>,
-+ <0x02000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x01e00000>,
-+ <0x03000000 0x1 0x00000000 0x1 0x00000000 0x0 0x40000000>;
-+ resets = <&cru SRST_PCIE_POWER_UP>, <&cru SRST_P_PCIE>;
-+ reset-names = "pwr", "pipe";
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ status = "disabled";
-+
-+ pcie_intc: legacy-interrupt-controller {
-+ interrupt-controller;
-+ interrupt-parent = <&gic>;
-+ interrupts = <GIC_SPI 155 IRQ_TYPE_EDGE_RISING>;
-+ #address-cells = <0>;
-+ #interrupt-cells = <1>;
-+ };
-+ };
-+
- gic: interrupt-controller@fed01000 {
- compatible = "arm,gic-400";
- reg = <0x0 0xfed01000 0 0x1000>,
--- /dev/null
+From 263fac6b09b42a1b077c21354370d38758237ab0 Mon Sep 17 00:00:00 2001
+From: Yao Zi <ziyao@disroot.org>
+Date: Thu, 18 Sep 2025 15:30:56 +0000
+Subject: [PATCH] arm64: dts: rockchip: Add PCIe Gen2x1 controller for RK3528
+
+Describes the PCIe Gen2x1 controller integrated in RK3528 SoC. The SoC
+doesn't provide a separate MSI controller, thus the one integrated in
+designware PCIe IP must be used.
+
+Signed-off-by: Yao Zi <ziyao@disroot.org>
+Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
+Link: https://patch.msgid.link/20250918153057.56023-3-ziyao@disroot.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3528.dtsi | 56 +++++++++++++++++++++++++++++++-
+ 1 file changed, 55 insertions(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+@@ -7,6 +7,7 @@
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
++#include <dt-bindings/phy/phy.h>
+ #include <dt-bindings/pinctrl/rockchip.h>
+ #include <dt-bindings/clock/rockchip,rk3528-cru.h>
+ #include <dt-bindings/power/rockchip,rk3528-power.h>
+@@ -294,10 +295,63 @@
+
+ soc {
+ compatible = "simple-bus";
+- ranges = <0x0 0xfe000000 0x0 0xfe000000 0x0 0x2000000>;
++ ranges = <0x0 0xfc000000 0x0 0xfc000000 0x0 0x44000000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
++ pcie: pcie@fe000000 {
++ compatible = "rockchip,rk3528-pcie",
++ "rockchip,rk3568-pcie";
++ reg = <0x0 0xfe000000 0x0 0x400000>,
++ <0x0 0xfe4f0000 0x0 0x010000>,
++ <0x0 0xfc000000 0x0 0x100000>;
++ reg-names = "dbi", "apb", "config";
++ bus-range = <0x0 0xff>;
++ clocks = <&cru ACLK_PCIE>, <&cru HCLK_PCIE_SLV>,
++ <&cru HCLK_PCIE_DBI>, <&cru PCLK_PCIE>,
++ <&cru CLK_PCIE_AUX>;
++ clock-names = "aclk_mst", "aclk_slv",
++ "aclk_dbi", "pclk",
++ "aux";
++ device_type = "pci";
++ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "sys", "pmc", "msg", "legacy", "err",
++ "msi";
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 0 7>;
++ interrupt-map = <0 0 0 1 &pcie_intc 0>,
++ <0 0 0 2 &pcie_intc 1>,
++ <0 0 0 3 &pcie_intc 2>,
++ <0 0 0 4 &pcie_intc 3>;
++ linux,pci-domain = <0>;
++ max-link-speed = <2>;
++ num-lanes = <1>;
++ phys = <&combphy PHY_TYPE_PCIE>;
++ phy-names = "pcie-phy";
++ power-domains = <&power RK3528_PD_VPU>;
++ ranges = <0x01000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x00100000>,
++ <0x02000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x01e00000>,
++ <0x03000000 0x1 0x00000000 0x1 0x00000000 0x0 0x40000000>;
++ resets = <&cru SRST_PCIE_POWER_UP>, <&cru SRST_P_PCIE>;
++ reset-names = "pwr", "pipe";
++ #address-cells = <3>;
++ #size-cells = <2>;
++ status = "disabled";
++
++ pcie_intc: legacy-interrupt-controller {
++ interrupt-controller;
++ interrupt-parent = <&gic>;
++ interrupts = <GIC_SPI 155 IRQ_TYPE_EDGE_RISING>;
++ #address-cells = <0>;
++ #interrupt-cells = <1>;
++ };
++ };
++
+ gic: interrupt-controller@fed01000 {
+ compatible = "arm,gic-400";
+ reg = <0x0 0xfed01000 0 0x1000>,
+++ /dev/null
-From 047bac0be317e68b89d0deed4f659f8e080df6e8 Mon Sep 17 00:00:00 2001
-From: Yao Zi <ziyao@disroot.org>
-Date: Thu, 18 Sep 2025 15:30:57 +0000
-Subject: [PATCH] arm64: dts: rockchip: Enable PCIe controller on Radxa E20C
-
-Radxa E20C provides one of its GbE ports through RTL8111H connected to
-SoC's PCIe controller. Let's enable the controller and the PHY used by
-it to allow usage of the port.
-
-Signed-off-by: Yao Zi <ziyao@disroot.org>
-Link: https://patch.msgid.link/20250918153057.56023-4-ziyao@disroot.org
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts | 12 ++++++++++++
- 1 file changed, 12 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
-@@ -171,6 +171,10 @@
- };
- };
-
-+&combphy {
-+ status = "okay";
-+};
-+
- &cpu0 {
- cpu-supply = <&vdd_arm>;
- };
-@@ -229,6 +233,14 @@
- };
- };
-
-+&pcie {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pciem1_pins>;
-+ reset-gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
-+ vpcie3v3-supply = <&vcc_3v3>;
-+ status = "okay";
-+};
-+
- &pinctrl {
- ethernet {
- gmac1_rstn_l: gmac1-rstn-l {
--- /dev/null
+From 047bac0be317e68b89d0deed4f659f8e080df6e8 Mon Sep 17 00:00:00 2001
+From: Yao Zi <ziyao@disroot.org>
+Date: Thu, 18 Sep 2025 15:30:57 +0000
+Subject: [PATCH] arm64: dts: rockchip: Enable PCIe controller on Radxa E20C
+
+Radxa E20C provides one of its GbE ports through RTL8111H connected to
+SoC's PCIe controller. Let's enable the controller and the PHY used by
+it to allow usage of the port.
+
+Signed-off-by: Yao Zi <ziyao@disroot.org>
+Link: https://patch.msgid.link/20250918153057.56023-4-ziyao@disroot.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
+@@ -171,6 +171,10 @@
+ };
+ };
+
++&combphy {
++ status = "okay";
++};
++
+ &cpu0 {
+ cpu-supply = <&vdd_arm>;
+ };
+@@ -229,6 +233,14 @@
+ };
+ };
+
++&pcie {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pciem1_pins>;
++ reset-gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
++ vpcie3v3-supply = <&vcc_3v3>;
++ status = "okay";
++};
++
+ &pinctrl {
+ ethernet {
+ gmac1_rstn_l: gmac1-rstn-l {
+++ /dev/null
-From: Shawn Lin <shawn.lin@rock-chips.com>
-To: Vinod Koul <vkoul@kernel.org>
-Cc: Kishon Vijay Abraham I <kishon@kernel.org>,
- Heiko Stuebner <heiko@sntech.de>, Yao Zi <ziyao@disroot.org>,
- linux-phy@lists.infradead.org,
- linux-rockchip@lists.infradead.org,
- Shawn Lin <shawn.lin@rock-chips.com>
-Subject: [PATCH] phy: rockchip: naneng-combphy: Fix PCIe L1ss support
-Date: Thu, 13 Nov 2025 11:00:28 +0800 [thread overview]
-Message-ID: <1763002828-212219-1-git-send-email-shawn.lin@rock-chips.com> (raw)
-
-Need to control the delay PLL turnoff time if PCIe works on
-L1 PM substates.
-
-Fixes: bbcca4fac873 ("phy: rockchip: naneng-combphy: Add RK3528 support")
-Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
----
-
- drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
---- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
-+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
-@@ -21,6 +21,9 @@
- #define REF_CLOCK_100MHz (100 * HZ_PER_MHZ)
-
- /* RK3528 COMBO PHY REG */
-+#define RK3528_PHYREG5 0x14
-+#define RK3528_PHYREG5_GATE_TX_PCK_SEL BIT(3)
-+#define RK3528_PHYREG5_GATE_TX_PCK_DLY_PLL_OFF BIT(3)
- #define RK3528_PHYREG6 0x18
- #define RK3528_PHYREG6_PLL_KVCO GENMASK(12, 10)
- #define RK3528_PHYREG6_PLL_KVCO_VALUE 0x2
-@@ -504,6 +507,11 @@ static int rk3528_combphy_cfg(struct roc
- case REF_CLOCK_100MHz:
- rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
- if (priv->type == PHY_TYPE_PCIE) {
-+ /* Gate_tx_pck_sel length select for L1ss support */
-+ rockchip_combphy_updatel(priv, RK3528_PHYREG5_GATE_TX_PCK_SEL,
-+ RK3528_PHYREG5_GATE_TX_PCK_DLY_PLL_OFF,
-+ RK3528_PHYREG5);
-+
- /* PLL KVCO tuning fine */
- val = FIELD_PREP(RK3528_PHYREG6_PLL_KVCO, RK3528_PHYREG6_PLL_KVCO_VALUE);
- rockchip_combphy_updatel(priv, RK3528_PHYREG6_PLL_KVCO, val,
projects / openwrt / openwrt.git / commitdiff